1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly, to a metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof.
2. Description of the Related Art
Increases in the integration density of semiconductor memory devices such as dynamic random access memory (DRAM) are typically accompanied by corresponding decreases in the area occupied by MOS transistors in the devices. As a result, the channel length of the MOS transistors is typically reduced, which may cause a short channel effect. When the short channel effect occurs in an access MOS transistor employed as a memory cell in a DRAM device, a threshold voltage of the DRAM cell decreases and leakage current increases, which degrades a refresh property of the DRAM device. Accordingly, a MOS transistor having a recessed gate electrode capable of suppressing the short channel effect by increasing the gate channel length, even when the integration density of the DRAM device is increased, has been developed.
In a MOS transistor having the recessed gate electrode, the semiconductor substrate may be partially recessed to form a gate in the recessed region and to form a channel in the silicon substrate at both sides of the gate.
FIG. 1 illustrates a cross-sectional view of a conventional MOS transistor having a recessed gate electrode.
Referring to FIG. 1, an active region A is disposed in a predetermined region of a semiconductor substrate 100. The active region A is defined by an isolation layer (not shown). A channel trench region 104 is disposed to cross a predetermined part of the active region A. A gate insulating layer 106 is disposed to cover the bottom and sidewalls of the channel trench region 104. A gate pattern 114 is disposed to fill the channel trench region 104, which is covered by the gate insulating layer 106, and to cross the active region A. The gate pattern 114 is composed of a polysilicon pattern 108, a tungsten silicide pattern 110 and a hard mask pattern 112. An insulating layer spacer 116 is formed to cover sidewalls of the gate pattern 114. Source and drain regions 118 are disposed within the active region A, below both sides of the gate pattern 114.
The MOS transistor having the recessed gate electrode shown in FIG. 1 has an outer gate shape in which the channel trench region 104 and the gate pattern 114 have the same width. The outer gate has a concentrated electric field at an upper corner of the active region adjacent to the polysilicon pattern 108, the upper corner marked by a dotted circle denoted by reference numeral 120. Due to the concentrated electric field, the threshold voltage property of the device is degraded and the leakage current is increased.
Methods for preventing electric field concentration at an upper corner of an active region adjacent to a gate polysilicon pattern have been developed. In one such method, the concentration of the electric field at the upper corner of the active region is prevented to reduce the leakage current. In particular, a main trench and a parasitic trench, adjacent to the main trench, are formed in a substrate. A thermal oxide layer is formed in the main trench and a gate oxide layer is formed in the parasitic trench relatively thicker than in other regions. A conductive layer for forming the gate electrode is buried within the trench.
While this method may prevent the concentration of the electric field at the upper corner of the active region so that leakage current can be suppressed, since the area of the active region decreases when the width of the top of the trench increases, the current drivability of the device is degraded.
In order to prevent the concentrated electric field of the outer gate and the decreased current drivability due to the increased top width of the trench, a method of forming an inner gate-type gate pattern in which the width of the gate pattern is smaller than the width of the trench has been proposed. However, the decreased gate size may result in misalignment, and a metal silicide layer formed on the polysilicon may be cracked when the surface of the metal silicide layer is not uniform.
Thus, a method of fabricating a MOS transistor having a recessed gate electrode which can prevent concentration of the electric field at an upper corner of an active region, and having a gate pattern whose top width is equal to the width of the channel trench region, is needed.